This invention relates to a dynamic RAM (random access memory) which is constructed of a MOS (metal-oxide-semiconductor) integrated circuit.
The dynamic RAM (hereinbelow, termed "D.RAM") includes a plurality of memory cells for storing information. The memory cell is constructed of, for example, a capacitor for storing the information in the form of charges, and an insulated-gate field effect transistor (hereinbelow, termed "MOSFET" or "MOS transistor") for selecting an address.
In the D.RAM which is formed on a semiconductor substrate, the charges stored in the capacitor within the memory cell decrease with time on account of leakage current etc. In other words, the information stored in the memory cell is lost with the lapse of time.
In order to normally keep correct information stored in the memory cell, it is necessary to perform the so-called refresh operation in which the information stored in the memory cell is read out before it is lost. This information is then amplified, and the amplified information is written into the same memory cell again.
The refresh operation of memory cells in a D.RAM of 64 kilobits can be carried out by a circuit having a self-refresh function as described in, for example, a Japanese magazine `Denshi Gijutsu (Electronics Technology)`, Vol. 23, No. 3, pp. 30-33. The D.RAM described in this article has an external terminal for the refresh control. When a refresh control REF of predetermined level is applied to the external terminal, a plurality of memory cells within the D.RAM are automatically refreshed. In this case, however, the external terminal for the refresh control must be disposed in the D.RAM. Thus, the cost of the device rises because of the requirement of having the external terminal for the refresh operation.
The D.RAM of 64 kilobits referred to above is adapted to operate with a single power source. Moreover, it reduces the number of external terminals to 16 by adopting an address multiplex system. That is, it is encased in a package of 16 pins.
The memory capacities of D.RAMs have become large with the progress of semiconductor integrated circuit technology etc. It has accordingly become possible to manufacture a D.RAM having a large capacity of, e.g., 256 kilobits.
The number of bits of address signals required for a D.RAM having such large capacity as 256 kilobits increases in comparison with that for a D.RAM of 64 kilobits. Therefore, even when the multiplex system is adopted for a D.RAM of 256 kilobits, it is difficult to install this D.RAM on the same package of 16 pins as that of the D.RAM of 64 kilobits. More specifically, a D.RAM of 256 kilobits employing the address multiplex system requires 9 pins for address signal terminals, 2 pins for address strobe signal terminals (RAS, CAS), 1 pin for a read/write signal terminal (WE), 1 pin for an output signal terminal (D.sub.OUT), 1 pin for an input signal terminal (D.sub.in) and 2 pins for power source terminals. These pins alone total 16. Therefore, if an additional pin is used for the refresh operation, a D.RAM of 256 kilobits becomes incompatible with a D.RAM of 64 kilobits. This makes it difficult for potential users of such a 256 kilobit D.RAM to utilize the device.
In order to permit the self-refresh operation described above, the D.RAM needs to be supplied with the refresh control signal REF. Therefore, a special external circuit for forming the refresh control signal REF must be disposed outside the D.RAM. The increased circuitry brought about by such an external circuit is undesirable. Moreover, the signal REF to be supplied to the external terminal of the D.RAM is delayed comparatively greatly in this case, which leads to the disadvantage that the access cycle of the memory becomes longer than is necessary. More specifically, wiring in a printed circuit board or the like, on which the D.RAM is installed, has a comparatively large wiring capacitance etc. and thus forms a heavy load. The signal delay accordingly develops in the wiring. This results in the restriction that the signal REF to be supplied to the D.RAM cannot be supllied at a high rate of speed due to inherent wiring delays.